Overview

The successful candidate shall utilize advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent analog matching performance, area and power requirements. He or she shall will be working on the latest process technologies. He or she shall work closely with circuit designers to generate high-quality layout in a highly efficient way.

Responsibilities

Work close with circuit designers to optimize the floor plan;
Perform daily layout editing, DRC/LVS tasks to ensure the quality of the layout;
Create a solid power grid for better power integrity;
Work with the circuit designers to optimize the quality of the layout, including but not limited to matching and signal integrity;
Employ efficient design methodologies to reduce the number of iterations and to deliver the product promptly.

Requirements

Mandatory Knowledge/Skills/Abilities:

Extremely familiar with layout editing tools, such as Virtuoso;
Highly proficient with DRC/LVS/ERC related tools and flows, such as Calibre, PVS (or IC Validator);
Have extensive experience designing layout in deep sub-micron CMOS technologies, especially FinFET technologies (7nm and 5nm);
Decent understanding in the issues of electro-migration and IR drop, RC delay, self-heating, capacitive cross-talk, etc.;
Decent understanding in analog layout requirements, such as matching and shielding;
Knowledge in automatic P&R or chip-level floor planning and chip-level layout integration.

Preferred Knowledge/Skill/Abilities:

Decent Understanding in analog design methodologies, including the use of layout constraints;
Knowledge in performing RC extraction and EM/IR analysis;
Knowledge in CAD tool setup and maintenance;
Ability to generate pCell and pyCell to facilitate layout design;
Excellent communication skills and team spirit to work with members across multiple sites and functionalities;
Experience in designing layout for high-speed, high-performance analog, and mixed-signal circuits.

Education and Experience Requirements: